1. Field of the Invention
The present invention relates to a bridge circuit.
2. Description of the Prior Art
It is known to transfer data between circuits using any number of different techniques. Two such known techniques are synchronous and asynchronous data transfer.
Where two circuits between which data being transferred operate at the same frequency, or the frequency of one circuit is an integer multiple of the other, then data can typically be transferred synchronously. During synchronous data transfer, a common clock signal provides timing information which is used to co-ordinate the data transfer between the circuits. The common clock signal is supplied to the circuits and the data transfer typically occurs with reference to a point during each clock cycle. For example, where the two circuits are coupled by a bus, then on the rising edge of the clock signal the transmitting circuit may drive a data value onto the bus and on the rising edge of the next clock signal the receiving circuit will capture that data value.
Where two circuits between which data being transferred operate at different frequencies (in which the frequency of one circuit is not an integer multiple of the other), then data is typically transferred asynchronously. To facilitate asynchronous data transfer a bridge circuit may be provided.
Bridge circuits are known and may be used as an interface between two circuits which typically process data at different data rates. The bridge circuit can receive data from a source circuit at a particular data rate and can then transmit that data onto a receiver circuit at another data rate, thereby facilitating the transfer of data between the two circuits.
One such known bridge circuit is illustrated with reference to FIG. 1A, the operation of that circuit is shown in FIG. 1B.
The bridge circuit 20 is provided between a processor core 10 and a memory 30. The bridge circuit 20 receives a clock signal CLK1 which is indicative of the data rate of data provided by the core 10 over the bus 15. The bridge circuit 20 also receives a clock signal CLK2 which is indicative of the data rate of data that can be received by the memory 30. The bridge circuit 20 has three registers 22, 24, 26 arranged in series between the data bus 15 and the data bus 45. The first register 22 is clocked by the clock signal CLK1, whereas the registers 24 and 26 receive the clock signal CLK2. These three registers 22, 24 26 facilitate the transfer of data between the data bus 15 and the data bus 45.
The operation of the bridge circuit 20 will now be described with reference to FIG. 1B.
Firstly, the operation of the register 22 will be described. At time t0 the data value A provided by the core 10 on the data bus 15 is clocked on the rising edge of the clock signal CLK1 into the register 22 and is then available on the data bus 25. Between times t0 and t1 the data value provided by the core 10 changes from data value A to data value B. At time t1 the data value B is latched into the register 22 and is then available on the data bus 25.
Next, the operation of the registers 24 and 26 will be described. At clock cycle 0 the data value provided on the bus 25 is latched into the register 24. Hence, data value A is latched into the register 24.
At clock cycle 1 the data value A is then latched into the register 26 and is subsequently available to the memory over the data bus 45. Also at clock cycle 1 the data value provided on the data bus 25 is latched into the register 24. However, because the data value provided on the data bus 25 transitions from data value A to data value B just before clock cycle 1, the data value provided to the register 26 is in an indeterminate state X for a period of time. However, prior to clock cycle 2 occurring the data value settles to data value B and at clock cycle 2 data value B is latched into the register 26. Hence, it will be appreciated that data values provided on by the core 10 can be available to the memory 30 with a latency of around only 3 clock cycles (e.g. data value A is available from the core 10 prior to clock cycle 0 and will be available to the memory 30 on the rising edge of clock cycle 2).
Accordingly, it can be seen that data values can be provided to the bridge circuit 20 at one data rate and then provided to the memory 30 at a different data rate, thereby enabling asynchronous data transmission to occur. Equally, data values can be provided to the bridge circuit 20 and then provided to the memory 30 at the same data rate. However, in either situation, the provision of the three registers in the bridge circuit 20 introduces a short latency to the data transfer. Although this latency is undesirable because it slows the data transfer, the provision of the three registers enables data to be reliably transferred between the core 10 and the memory 30 since the clocking arrangement ensures that any indeterminate states have settled prior to the data values being provided by the bridge circuit to the devices between which it is coupled
It is an object of the present invention to provide an improved bridge circuit.